Stop the war!
Остановите войну!
for scientists:
default search action
"Experimental Analysis and FPGA Implementation of the Real Valued Time ..."
Soner Yesil, Cansu Sen, Ali Özgür Yilmaz (2019)
- Soner Yesil, Cansu Sen, Ali Özgür Yilmaz:
Experimental Analysis and FPGA Implementation of the Real Valued Time Delay Neural Network Based Digital Predistortion. ICECS 2019: 614-617
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.