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"Design of a phase alignment circuit for lock in amplifiers in ..."

M. Yerena-Mora et al. (2019)

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DOI: 10.1109/ICECS46596.2019.8965035

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-21

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  dblp key:
  - conf/icecsys/Yerena-MoraCSCM19
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  - https://dblp.org/rec/conf/icecsys/Yerena-MoraCSCM19
M. Yerena-Mora, Oscar J. Cinco-Izquierdo, María Teresa Sanz-Pascual, Belén Calvo López, A. Márquez:
Design of a phase alignment circuit for lock in amplifiers in 1.8V-0.18μm CMOS technology. ICECS 2019: 695-698

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