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"A gate-level timing model for SOI circuits."

Mehrdad Shahriari, Farid N. Najm (2001)

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DOI: 10.1109/ICECS.2001.957594

access: closed

type: Conference or Workshop Paper

metadata version: 2021-01-18

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  - conf/icecsys/ShahriariN01
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Mehrdad Shahriari, Farid N. Najm:
A gate-level timing model for SOI circuits. ICECS 2001: 795-798

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