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"DLX HOTOKADA: A design and implementation of a 32-bit dual core capable ..."

Darryl Aldrin M. Dioquino et al. (2008)

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DOI: 10.1109/ICECS.2008.4674891

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-23

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  - conf/icecsys/DioquinoRSZBR08
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  - https://dblp.org/rec/conf/icecsys/DioquinoRSZBR08
Darryl Aldrin M. Dioquino, Katrina Joy S. Rosario, Homer F. Supe, Jestoni V. Zarsuela, Anastacia P. Ballesil, Joy Alinda Reyes:
DLX HOTOKADA: A design and implementation of a 32-bit dual core capable DLX microprocessor with single level cache. ICECS 2008: 466-469

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