"Target-Aware Automated RTL Generation for RISC-V SoC Designs: A ..."

Mohamed Badawy et al. (2025)

> Home

Details and statistics

DOI: 10.1109/ICECS66544.2025.11270631

access: closed

type: Conference or Workshop Paper

metadata version: 2026-01-16

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/icecsys/BadawyWSE25
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/icecsys/BadawyWSE25
Mohamed Badawy, Jiulong Wang, Paritosh Kumar Sinha, Wolfgang Ecker:
Target-Aware Automated RTL Generation for RISC-V SoC Designs: A Model-Driven Approach. ICECS 2025: 1-2

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.