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"A 24 Gbps SerDes transceiver for on-chip networks using a new ..."

Ramy N. Tadros et al. (2015)

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DOI: 10.1109/ICEAC.2015.7352168

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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Ramy N. Tadros, Ahmed H. Abdelrahman, Maged Ghoneima, Yehea Ismail:
A 24 Gbps SerDes transceiver for on-chip networks using a new half-data-rate self-timed 3-level signaling scheme. ICEAC 2015: 1-4

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