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"A 64-bit floating-point processing unit with a horizontal instruction code ..."

Akira Katsuno et al. (1990)

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DOI: 10.1109/ICCD.1990.130250

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  dblp key:
  - conf/iccd/KatsunoTKSSG90
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  - https://dblp.org/rec/conf/iccd/KatsunoTKSSG90
Akira Katsuno, Hiromasa Takahashi, Hajime Kubosawa, Tomio Sato, Atsuhiro Suga, Gensuke Goto:
A 64-bit floating-point processing unit with a horizontal instruction code for parallel operations. ICCD 1990: 347-350

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