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"A bipartition-codec architecture to reduce power in pipelined circuits."

Shanq-Jang Ruan et al. (1999)

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DOI: 10.1109/ICCAD.1999.810627

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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  dblp key:
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  persistent URL:
  - https://dblp.org/rec/conf/iccad/RuanSLCH99
Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Shyh-Jong Chen, Xian-Jun Huang:
A bipartition-codec architecture to reduce power in pipelined circuits. ICCAD 1999: 84-90

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