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"A FPGA implementation of a parallel Viterbi decoder for block cyclic and ..."

Jeffrey S. Reeve, Kosala Amarasinghe (2004)

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DOI: 10.1109/ICC.2004.1313001

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-25

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Jeffrey S. Reeve, Kosala Amarasinghe:
A FPGA implementation of a parallel Viterbi decoder for block cyclic and convolution codes. ICC 2004: 2596-2599

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