Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"A digital signal processor module architecture and its implementation ..."

K. Okada et al. (1984)

> Home

Details and statistics

DOI: 10.1109/ICASSP.1984.1172728

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-19

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/icassp/OkadaESYSI84
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/icassp/OkadaESYSI84
K. Okada, T. Ehara, H. Suzuki, K. Yanagida, K. Saito, N. Ichiura:
A digital signal processor module architecture and its implementation using VLSIs. ICASSP 1984: 378-381

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.