"High speed algorithm and VLSI architecture design for decoding BCH product ..."

Zhipei Chi, Keshab K. Parhi (2002)

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DOI: 10.1109/ICASSP.2002.5745302

access: closed

type: Conference or Workshop Paper

metadata version: 2024-05-07

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Zhipei Chi, Keshab K. Parhi:
High speed algorithm and VLSI architecture design for decoding BCH product codes. ICASSP 2002: 3089-3092

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