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"A Parallel Simulated Annealing Approach for Floorplanning in VLSI."
Jyh-Perng Fang et al. (2009)
- Jyh-Perng Fang, Yang-Lang Chang, Chih-Chia Chen, Wen-Yew Liang, Tung-Ju Hsieh, Muhammad T. Satria, Chin-Chuan Han:
A Parallel Simulated Annealing Approach for Floorplanning in VLSI. ICA3PP 2009: 291-302
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