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"Automatic Hardware Synthesis of Nested Loops Using UET Grids and VHDL."

Nectarios Koziris et al. (1997)

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DOI: 10.1007/BFB0031660

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-22

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  - conf/hpcn/KozirisAEPT97
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  - https://dblp.org/rec/conf/hpcn/KozirisAEPT97
Nectarios Koziris, Theodore Andronikos, George Economakos, George K. Papakonstantinou, Panayotis Tsanakas:
Automatic Hardware Synthesis of Nested Loops Using UET Grids and VHDL. HPCN Europe 1997: 888-897

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