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"FPGA Accelerated NoC-Simulation: A Case Study on the Intel Xeon Phi ..."

Oliver Jakob Arndt et al. (2017)

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DOI: 10.1145/3120895.3120916

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-14

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  dblp key:
  - conf/heart/ArndtSWPNB17
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  - https://dblp.org/rec/conf/heart/ArndtSWPNB17
Oliver Jakob Arndt, Christian Spindeldreier, Kevin Wohnrade, Daniel Pfefferkorn, Martin Neuenhahn, Holger Blume:
FPGA Accelerated NoC-Simulation: A Case Study on the Intel Xeon Phi Ringbus Topology. HEART 2017: 21:1-21:6

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