"Inductance-aware Clock Network Synthesis Considering Hierarchical ..."

Jindong Zhou et al. (2025)

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DOI: 10.1145/3716368.3735164

access: closed

type: Conference or Workshop Paper

metadata version: 2025-07-06

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Jindong Zhou, Zi'Ang Ge, Chenbo Xi, Pingqiang Zhou:
Inductance-aware Clock Network Synthesis Considering Hierarchical Interconnects in 3D ICs. ACM Great Lakes Symposium on VLSI 2025: 619-625

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