"An efficient cut enumeration for depth-optimum technology mapping for ..."

Taiga Takata, Yusuke Matsunaga (2009)

> Home

Details and statistics

DOI: 10.1145/1531542.1531622

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/glvlsi/TakataM09
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/glvlsi/TakataM09
Taiga Takata, Yusuke Matsunaga:
An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs. ACM Great Lakes Symposium on VLSI 2009: 351-356

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.