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"An algorithm-base fault tolerance (more than one error) using concurrent ..."

Chin-Chien Sha, R. W. Leavene (1994)

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DOI: 10.1109/GLSV.1994.289995

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

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Chin-Chien Sha, R. W. Leavene:
An algorithm-base fault tolerance (more than one error) using concurrent error detection for FFT processors. Great Lakes Symposium on VLSI 1994: 56-61

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