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"Robust wiring networks for DfY considering timing constraints."
Philipp V. Panitz et al. (2007)
- Philipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl:
Robust wiring networks for DfY considering timing constraints. ACM Great Lakes Symposium on VLSI 2007: 43-48
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