Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Reducing parity generation latency through input value aware circuits."

Yusuf Osmanlioglu, Yusuf Onur Koçberber, Oguz Ergin (2009)

> Home

Details and statistics

DOI: 10.1145/1531542.1531570

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-14

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/glvlsi/OsmanliogluKE09
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/glvlsi/OsmanliogluKE09
Yusuf Osmanlioglu, Yusuf Onur Koçberber, Oguz Ergin:
Reducing parity generation latency through input value aware circuits. ACM Great Lakes Symposium on VLSI 2009: 109-112

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.