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"Hardware-efficient propagate partial sad architecture for variable block ..."

Zhenyu Liu et al. (2007)

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DOI: 10.1145/1228784.1228826

access: closed

type: Conference or Workshop Paper

metadata version: 2020-11-23

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Zhenyu Liu, Yiqing Huang, Yang Song, Satoshi Goto, Takeshi Ikenaga:
Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC. ACM Great Lakes Symposium on VLSI 2007: 160-163

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