"Improved timing closure by early buffer planning in floor-placement design ..."

Ali Jahanian, Morteza Saheb Zamani (2007)

> Home

Details and statistics

DOI: 10.1145/1228784.1228916

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/glvlsi/JahanianZ07
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/glvlsi/JahanianZ07
Ali Jahanian, Morteza Saheb Zamani:
Improved timing closure by early buffer planning in floor-placement design flow. ACM Great Lakes Symposium on VLSI 2007: 558-563

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.