"40 MHz 0.25 um CMOS embedded 1T bit-line decoupled DRAM FIFO for ..."

Michael I. Fuller et al. (2003)

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DOI: 10.1145/764808.764855

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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Michael I. Fuller, James P. Mabry, John A. Hossack, Travis N. Blalock:
40 MHz 0.25 um CMOS embedded 1T bit-line decoupled DRAM FIFO for mixed-signal applications. ACM Great Lakes Symposium on VLSI 2003: 182-185

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