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"Performance enhancement in phased logic circuits using automatic ..."

Kenneth Fazel et al. (2004)

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DOI: 10.1145/988952.989051

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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Kenneth Fazel, Lun Li, Mitchell A. Thornton, Robert B. Reese, Cherrice Traver:
Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion. ACM Great Lakes Symposium on VLSI 2004: 413-416

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