"Efficient selection and analysis of critical-reliability paths and gates."

Jifeng Chen, Shuo Wang, Mohammad Tehranipoor (2012)

> Home

Details and statistics

DOI: 10.1145/2206781.2206793

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/glvlsi/ChenWT12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/glvlsi/ChenWT12
Jifeng Chen, Shuo Wang, Mohammad Tehranipoor:
Efficient selection and analysis of critical-reliability paths and gates. ACM Great Lakes Symposium on VLSI 2012: 45-50

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.