Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Efficient Method for Timing-based Information Flow Verification in ..."

Khitam M. Alatoun, Ranga Vemuri (2022)

> Home

Details and statistics

DOI: 10.1145/3526241.3530363

access: closed

type: Conference or Workshop Paper

metadata version: 2022-06-03

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/glvlsi/AlatounV22
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/glvlsi/AlatounV22
Khitam M. Alatoun, Ranga Vemuri:
Efficient Method for Timing-based Information Flow Verification in Hardware Designs. ACM Great Lakes Symposium on VLSI 2022: 159-163

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.