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"Parallel optimization of transistor level circuits using cartesian genetic ..."

Vojtech Mrazek, Zdenek Vasícek (2017)

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DOI: 10.1145/3067695.3084212

access: closed

type: Conference or Workshop Paper

metadata version: 2019-09-16

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  dblp key:
  - conf/gecco/MrazekV17
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Vojtech Mrazek, Zdenek Vasícek:
Parallel optimization of transistor level circuits using cartesian genetic programming. GECCO (Companion) 2017: 1849-1856

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