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"A Tool for Translation of VHDL Descriptions into a Formal Model and its ..."

Rajesh K. Bawa, Emmanuelle Encrenaz (1996)

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DOI: 10.1007/3-540-61648-9_59

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-22

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  dblp key:
  - conf/ftrtft/BawaE96
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  - https://dblp.org/rec/conf/ftrtft/BawaE96
Rajesh K. Bawa, Emmanuelle Encrenaz:
A Tool for Translation of VHDL Descriptions into a Formal Model and its Application to Formal Verification and Synthesis. FTRTFT 1996: 471-474

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