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"A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based ..."

E. Syam Sundar Reddy et al. (2004)

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DOI: 10.1109/FPT.2004.1393259

access: closed

type: Conference or Workshop Paper

metadata version: 2020-09-10

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E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Vijaykrishnan Narayanan:
A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs. FPT 2004: 121-128

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