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"A logic cell architecture exploiting the shannon expansion for the ..."

Qian Zhao et al. (2014)

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DOI: 10.1109/FPL.2014.6927460

access: closed

type: Conference or Workshop Paper

metadata version: 2017-10-18

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Qian Zhao, Kyosei Yanagida, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory. FPL 2014: 1-6

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