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ORCID"Altering LUT configuration for wear-out mitigation of FPGA-mapped designs."
Parthasarathy M. B. Rao et al. (2013)
- Parthasarathy M. B. Rao, Abdulazim Amouri, Saman Kiamehr, Mehdi Baradaran Tahoori:
Altering LUT configuration for wear-out mitigation of FPGA-mapped designs. FPL 2013: 1-8
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