Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"FPGA Implementation of an Area-Time Efficient FIR Filter Core Using a ..."

J. Javier Martínez et al. (2005)

> Home

Details and statistics

DOI: 10.1109/FPL.2005.1515782

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

- view
  authority control:
- export record
  dblp key:
  - conf/fpl/MartinezTGF05
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpl/MartinezTGF05
J. Javier Martínez, F. Javier Toledo, F. Javier Garrigós, José Manuel Ferrández de Vicente:
FPGA Implementation of an Area-Time Efficient FIR Filter Core Using a Self-Clocked Approach. FPL 2005: 547-550

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.