Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Combining data reuse exploitationwith data-level parallelization for FPGA ..."

Qiang Liu et al. (2008)

> Home

Details and statistics

DOI: 10.1109/FPL.2008.4629928

access: closed

type: Conference or Workshop Paper

metadata version: 2024-08-05

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/fpl/LiuCMC08
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpl/LiuCMC08
Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung:
Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework. FPL 2008: 179-184

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.