Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA."

Hoang Le, Weirong Jiang, Viktor K. Prasanna (2008)

> Home

Details and statistics

DOI: 10.1109/FPL.2008.4629921

access: closed

type: Conference or Workshop Paper

metadata version: 2017-06-02

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/fpl/LeJP08
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpl/LeJP08
Hoang Le, Weirong Jiang, Viktor K. Prasanna:
Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA. FPL 2008: 137-142

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.