"FPGA interconnect design using logical effort."

Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong (2008)

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DOI: 10.1145/1344671.1344710

access: closed

type: Conference or Workshop Paper

metadata version: 2025-01-19

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Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong:
FPGA interconnect design using logical effort. FPGA 2008: 257

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