"Clock power reduction for virtex-5 FPGAs."

Qiang Wang, Subodh Gupta, Jason Helge Anderson (2009)

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DOI: 10.1145/1508128.1508132

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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Qiang Wang, Subodh Gupta, Jason Helge Anderson:
Clock power reduction for virtex-5 FPGAs. FPGA 2009: 13-22

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