"Intra-masking dual-rail memory on LUT implementation for tamper-resistant ..."

Anh-Tuan Hoang, Takeshi Fujino (2012)

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DOI: 10.1145/2145694.2145696

access: closed

type: Conference or Workshop Paper

metadata version: 2025-01-19

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Anh-Tuan Hoang, Takeshi Fujino:
Intra-masking dual-rail memory on LUT implementation for tamper-resistant AES on FPGA. FPGA 2012: 1-10

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