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"Silicon Verification using High-Level Design Tools (Abstract Only)."

Tomasz S. Czajkowski (2015)

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DOI: 10.1145/2684746.2689131

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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  dblp key:
  - conf/fpga/Czajkowski15
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Tomasz S. Czajkowski:
Silicon Verification using High-Level Design Tools (Abstract Only). FPGA 2015: 272

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