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"Exploiting algorithmic-level memory parallelism in distributed ..."

Yu Bai et al. (2013)

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DOI: 10.1145/2435264.2435333

access: closed

type: Conference or Workshop Paper

metadata version: 2019-05-02

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  - conf/fpga/BaiFLR13
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Yu Bai, Abigail Fuentes-Rivera, Mingjie Lin, Mike Riera:
Exploiting algorithmic-level memory parallelism in distributed logic-memory architecture through hardware-assisted dynamic graph (abstract only). FPGA 2013: 273

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