"Formal Verification of Timed VHDL Programs."

Abdelrezzak Bara et al. (2010)

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type: Conference or Workshop Paper

metadata version: 2021-01-15

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  dblp key:
  - conf/fdl/BaraBCLER10
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  persistent URL:
  - https://dblp.org/rec/conf/fdl/BaraBCLER10
Abdelrezzak Bara, Pirouz Bazargan-Sabet, Remy Chevallier, Dominique Le Dû, Emmanuelle Encrenaz, Patricia Renault:
Formal Verification of Timed VHDL Programs. FDL 2010: 80-85

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