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"Exploring Performance and Cost Optimization with ASIC-Based CXL Memory."

Yupeng Tang et al. (2024)

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DOI: 10.1145/3627703.3650061

access: closed

type: Conference or Workshop Paper

metadata version: 2024-04-24

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  dblp key:
  - conf/eurosys/TangZZHYXLSHZCZ24
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  persistent URL:
  - https://dblp.org/rec/conf/eurosys/TangZZHYXLSHZCZ24
Yupeng Tang, Ping Zhou, Wenhui Zhang, Henry Hu, Qirui Yang, Hao Xiang, Tongping Liu, Jiaxin Shan, Ruoyun Huang, Cheng Zhao, Cheng Chen, Hui Zhang, Fei Liu, Shuai Zhang, Xiaoning Ding, Jianjun Chen:
Exploring Performance and Cost Optimization with ASIC-Based CXL Memory. EuroSys 2024: 818-833

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