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"New layout design methodology for monolithically integrated 3D CMOS logic ..."

Chika Tanaka, Keiji Ikeda, Masumi Saitoh (2015)

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DOI: 10.1109/ESSDERC.2015.7324763

access: closed

type: Conference or Workshop Paper

metadata version: 2020-10-25

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Chika Tanaka, Keiji Ikeda, Masumi Saitoh:
New layout design methodology for monolithically integrated 3D CMOS logic circuits based on parasitics engineering. ESSDERC 2015: 258-261

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