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"An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with wide range threshold ..."

Kentaro Yoshioka et al. (2012)

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DOI: 10.1109/ESSCIRC.2012.6341365

access: closed

type: Conference or Workshop Paper

metadata version: 2022-12-07

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Kentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro:
An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator. ESSCIRC 2012: 381-384

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