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"120V/ns output slew rate enhancement technique and high voltage clamping ..."

Hsiang-An Yang et al. (2015)

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DOI: 10.1109/ESSCIRC.2015.7313884

access: closed

type: Conference or Workshop Paper

metadata version: 2019-09-16

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  dblp key:
  - conf/esscirc/YangCLCCMCWLLLT15
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  - https://dblp.org/rec/conf/esscirc/YangCLCCMCWLLLT15
Hsiang-An Yang, Chao-Chang Chiu, Shin-Chi Lai, Jui-Lung Chen, Chih-Wei Chang, Che-Hao Meng, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Chao-Cheng Lee, Jian-Ru Lin, Tsung-Yen Tsai, Hsin-Yu Luo:
120V/ns output slew rate enhancement technique and high voltage clamping circuit in high integrated gate driver for power GaN FETs. ESSCIRC 2015: 291-294

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