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"Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power ..."

David Levacq et al. (2007)

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DOI: 10.1109/ESSCIRC.2007.4430277

access: closed

type: Conference or Workshop Paper

metadata version: 2024-03-11

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  - conf/esscirc/LevacqYKTS07
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David Levacq, Muhammad Yazid, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai:
Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution. ESSCIRC 2007: 190-193

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