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"A 1.5V 13bit 130-300MS/s self-calibrated DAC with active output stage and ..."

Martin Clara et al. (2008)

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DOI: 10.1109/ESSCIRC.2008.4681842

access: closed

type: Conference or Workshop Paper

metadata version: 2020-09-25

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  - conf/esscirc/ClaraKGMSP08
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Martin Clara, Wolfgang Klatzer, Daniel Gruber, Arnold Marak, Berthold Seger, Wolfgang Pribyl:
A 1.5V 13bit 130-300MS/s self-calibrated DAC with active output stage and 50MHz signal bandwidth in 0.13μm CMOS. ESSCIRC 2008: 262-265

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