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"Fully integrated, high performance triple SD PLL (2.2Ghz to 4.4Ghz) with ..."

Stefano Cipriani et al. (2008)

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DOI: 10.1109/ESSCIRC.2008.4681868

access: closed

type: Conference or Workshop Paper

metadata version: 2020-09-25

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  - conf/esscirc/CiprianiDPCBCAG08
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  - https://dblp.org/rec/conf/esscirc/CiprianiDPCBCAG08
Stefano Cipriani, Eric Duvivier, Gianni Puccio, Lorenzo Carpineto, Biagio Bisanti, Francesco Coppola, Martin Alderton, Jeremy Goldblatt:
Fully integrated, high performance triple SD PLL (2.2Ghz to 4.4Ghz) with minimized interaction. ESSCIRC 2008: 366-369

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