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"A 2GHz 2-bit Continuous-Time Delta Sigma ADC with 2GHz chopper achieving ..."

Pierluigi Cenci et al. (2022)

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DOI: 10.1109/ESSCIRC55480.2022.9911312

access: closed

type: Conference or Workshop Paper

metadata version: 2022-11-04

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  dblp key:
  - conf/esscirc/CenciBBGBRGBSB22
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  - https://dblp.org/rec/conf/esscirc/CenciBBGBRGBSB22
Pierluigi Cenci, Hans Brekelmans, Shagun Bajoria, Marcello Ganzerli, Bernard Burdiek, Robert Rutten, Yihan Gao, Muhammed Bolatkale, Paul Swinkels, Lucien J. Breems:
A 2GHz 2-bit Continuous-Time Delta Sigma ADC with 2GHz chopper achieving 12nV/sqrt(Hz) 1/f noise at 153kHz and -104.7dBc THD in 30MHz BW. ESSCIRC 2022: 321-324

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