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"Delay partitioning helps reducing variability in 3DVLSI."

A. Ayres et al. (2016)

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DOI: 10.1109/ESSCIRC.2016.7598246

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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  dblp key:
  - conf/esscirc/AyresRBFV16
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  - https://dblp.org/rec/conf/esscirc/AyresRBFV16
A. Ayres, Olivier Rozeau, B. Borot, Laurent Fesquet, Maud Vinet:
Delay partitioning helps reducing variability in 3DVLSI. ESSCIRC 2016: 75-78

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