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"Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS."

Oskar Andersson et al. (2013)

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DOI: 10.1109/ESSCIRC.2013.6649106

access: closed

type: Conference or Workshop Paper

metadata version: 2024-05-07

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  - conf/esscirc/AnderssonMMBR13
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Oskar Andersson, Babak Mohammadi, Pascal Meinerzhagen, Andreas Burg, Joachim Neves Rodrigues:
Dual-VT 4kb sub-VT memories with <1 pW/bit leakage in 65 nm CMOS. ESSCIRC 2013: 197-200

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