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"Design of Memory Access Module for YOLO v2 Neural Network Accelerator ..."

Jun Li et al. (2020)

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DOI: 10.1145/3443467.3443831

access: closed

type: Conference or Workshop Paper

metadata version: 2023-08-04

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  dblp key:
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  - https://dblp.org/rec/conf/eitce/LiLWY20
Jun Li, Ying Liang, Shengkai Wang, Jun Yang:
Design of Memory Access Module for YOLO v2 Neural Network Accelerator Based on FPGA. EITCE 2020: 658-662

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